1. Field Of The Invention
This invention relates to flash EEPROM memory arrays, and more particularly, to methods and apparatus for providing error management for such arrays.
2. History Of The Prior Art
Recently, flash (flash EEPROM memory) has been used as a new form of long term storage. A flash EEPROM memory array is constructed of a large plurality of floating-gate metal-oxide-silicon field effect transistor devices arranged as memory cells in typical row and column fashion with circuitry for accessing individual cells and placing the memory transistors of those cells in different memory conditions. Such memory transistors may be programmed by storing a charge on the floating gate. This charge remains when power is removed from the array. The charge level may be detected by interrogating the devices. These arrays may be designed to provide a smaller lighter functional equivalent of a hard disk drive which operates more rapidly and is not as sensitive to physical damage. Flash EEPROM memory arrays are especially useful in portable computers where space is at a premium and weight is extremely important.
As originally devised, each flash EEPROM memory device stores a single bit of data. If a flash EEPROM memory device is programmed so that charge is stored on the floating gate, the state is typically referred to as a "zero" or programmed state; while if little or no charge is stored on the gate, this is typically considered a "one" or erased state. Recently, it has been discovered that the transistor devices used for flash EEPROM memory arrays may be made to store charge at a number of distinct levels greater than the charge level of the erased state. Essentially, four or more distinct levels of charge (including the erased level) may be stored on the floating gates of the devices during programming and erasing by varying the voltages applied to the terminals of the devices and the duration of application; and these different charge levels (device conditions or states) may be detected. This allows flash EEPROM devices in memory arrays to store more than one bit per device and radically increases the storage capacity of such arrays. A device used in this manner is referred to as a multi-bit cell.
There are a number of problems which arise from the storage of more than one bit of data in a flash EEPROM cell. Because the maximum charge which may be stored is essentially fixed for any particular memory device, the differences between charge levels which indicate the different data values stored by the cell are much smaller when a number of levels are stored. The different charge levels are sensed by comparison to charge levels on reference cells. Over time, charge tends to leak from the floating gates of some of the memory devices. What would be relatively minor leakage from the floating gate of a device storing only a single bit of data may change the charge level of a multi-bit cell sufficiently to produce an incorrect value for comparison to a reference charge level. Consequently, there is chance for more errors to be caused by charge leakage from the floating gates of individual flash EEPROM cells arranged to store a number of different charge levels.
It is desirable to be able to correct errors caused by leakage from the floating gates of flash EEPROM memory devices so that those errors do not affect the accuracy of data stored.